From faa4bad2232e79b7addf9144bbcf725b7bfd401c Mon Sep 17 00:00:00 2001
From: Yinan Xu <xuyinan@ict.ac.cn>
Date: Tue, 20 Oct 2026 20:06:51 +0800
Subject: [PATCH] Bump difftest and Chisel to 7.14.0

---
 build.mill | 4 ++--
 difftest   | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/build.mill b/build.mill
index bf472f18..2fb09a81 100644
--- a/build.mill
+++ b/build.mill
@@ -7,8 +7,8 @@ val pwd = os.Path(sys.env("MILL_WORKSPACE_ROOT"))
 
 object ivys {
   val scala = "2.13.14"
-  val chisel = mvn"org.chipsalliance::chisel:7.11.0"
-  val chiselPlugin = mvn"org.chipsalliance:::chisel-plugin:7.11.0"
+  val chisel = mvn"org.chipsalliance::chisel:7.14.0"
+  val chiselPlugin = mvn"org.chipsalliance:::chisel-plugin:7.14.0"
 }
 
 trait CommonModule extends ScalaModule {
diff --git a/difftest b/difftest
index 29e80f85..268b88c6 160000
--- a/difftest
+++ b/difftest
@@ -1 +1 @@
-Subproject commit 29e80f8525735d1cb77f30fd2a3ea5eff3e6528c
+Subproject commit 268b88c6afde88881fd64d3f19f9d2cd2b747160