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Bump difftest and Chisel to 7.14.0 #287

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Bump difftest and Chisel to 7.14.0 #287

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4 changes: 2 additions & 2 deletions build.mill
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Original file line number Diff line number Diff line change
Expand Up @@ -7,8 +7,8 @@ val pwd = os.Path(sys.env("MILL_WORKSPACE_ROOT"))

object ivys {
val scala = "2.13.14"
val chisel = mvn"org.chipsalliance::chisel:7.11.0"
val chiselPlugin = mvn"org.chipsalliance:::chisel-plugin:7.11.0"
val chisel = mvn"org.chipsalliance::chisel:7.14.0"
val chiselPlugin = mvn"org.chipsalliance:::chisel-plugin:7.14.0"
}

trait CommonModule extends ScalaModule {
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2 changes: 1 addition & 1 deletion difftest
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Submodule difftest updated 44 files
+1 −1 AGENTS.md
+28 −0 Makefile
+108 −1 docs/test.md
+9 −12 docs/workflow.md
+29 −0 fpga.mk
+9 −4 palladium.mk
+10 −1 scripts/fpga/release.sh
+25 −0 src/main/scala/Bundles.scala
+42 −0 src/main/scala/Difftest.scala
+2 −2 src/main/scala/Replay.scala
+7 −5 src/main/scala/Squash.scala
+90 −0 src/main/scala/util/Hash.scala
+177 −0 src/main/scala/util/MatrixHash.scala
+172 −0 src/main/scala/util/StoreHash.scala
+25 −0 src/test/csrc/common/args.cpp
+2 −0 src/test/csrc/common/args.h
+1 −1 src/test/csrc/common/elfloader.cpp
+16 −0 src/test/csrc/common/matrix_hash.h
+38 −0 src/test/csrc/common/ram.cpp
+13 −3 src/test/csrc/common/ram.h
+37 −0 src/test/csrc/difftest/checkers.h
+1 −1 src/test/csrc/difftest/checkers/instructions.cpp
+198 −100 src/test/csrc/difftest/checkers/matrix.cpp
+49 −1 src/test/csrc/difftest/checkers/store.cpp
+3 −0 src/test/csrc/difftest/diffstate.cpp
+13 −3 src/test/csrc/difftest/diffstate.h
+52 −20 src/test/csrc/difftest/difftest.cpp
+3 −0 src/test/csrc/difftest/difftest.h
+12 −15 src/test/csrc/difftest/difftrace.cpp
+55 −4 src/test/csrc/difftest/refproxy.h
+68 −8 src/test/csrc/emu/emu.cpp
+5 −0 src/test/csrc/emu/emu.h
+5 −0 src/test/csrc/emu/simulator.h
+14 −4 src/test/csrc/fpga/fpga_main.cpp
+18 −0 src/test/csrc/fpga/fpga_transport.h
+6 −0 src/test/csrc/fpga/xdma.cpp
+8 −9 src/test/csrc/fpga/xdma.h
+552 −0 src/test/csrc/plugin/uvhs-gbus/gbus_transport.cpp
+65 −0 src/test/csrc/plugin/uvhs-gbus/gbus_transport.h
+137 −0 src/test/csrc/plugin/uvhs-gbus/uvaps_gbus_runtime.h
+5 −1 src/test/csrc/vcs/vcs_main.cpp
+8 −0 src/test/csrc/verilator/verilator.h
+8 −1 src/test/vsrc/common/DifftestClockGate.v
+2 −2 verilator.mk
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