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gf12: tighten ibex and ca53 clock periods so setup WS < 0 - #4702

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eder-matheus wants to merge 2 commits into
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The-OpenROAD-Project-staging:tightening_designs
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eder-matheus wants to merge 2 commits into
The-OpenROAD-Project:masterfrom
The-OpenROAD-Project-staging:tightening_designs

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@eder-matheus

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gf12/ibex

  • Remove SETUP_SLACK_MARGIN (180) and HOLD_SLACK_MARGIN (50). The flow
    only times the BC corner, so the margins over-repaired at BC without
    closing WC. Removing them cut area 18%, power 32% and flow runtime
    from 966 s to 307 s.
  • Clock period 1020 -> 840 ps.
    Finish: setup WS -34 ps, TNS -9.4 ns (493 endpoints), hold clean, 0 DRC.

gf12/ca53

  • Add constraint.sdc, which sources the platform SDC and redefines clk.
    Point SDC_FILE to it. The platform SDC is unchanged.
  • Clock period 2000 -> 1550 ps.
    Finish: setup WS -98.6 ps, TNS -0.8 ns (16 endpoints, worst is a
    clock-gate enable path), 0 DRC. Hold WS -25 ps (-15 ps in CI before).

Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
@eder-matheus eder-matheus self-assigned this Oct 19, 2026

@gemini-code-assist gemini-code-assist Bot left a comment

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Code Review

This pull request updates the SDC file path and constraints for the ca53 design, and adjusts the clock period and slack margins for the ibex design. A critical issue was identified in the new ca53 constraint file, where redefining the clock after sourcing the base SDC can invalidate existing clock-associated constraints in STA tools. It is recommended to set the clock period before sourcing the base SDC.

Comment on lines +1 to +4
source $::env(PLATFORM_DIR)/ca53_cpu/sdc/ca53_cpu.sdc

set clk_period 1550
create_clock -name clk -period $clk_period [get_ports clk]

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high

Redefining a clock using create_clock after sourcing the base SDC (ca53_cpu.sdc) can be highly problematic in STA tools like OpenSTA. When create_clock is called on an existing clock port/name, the tool destroys the original clock object and creates a new one. This action typically clears or invalidates any clock-associated constraints (such as set_input_delay, set_output_delay, set_clock_uncertainty, or set_clock_latency) that were defined in ca53_cpu.sdc and bound to the original clock.

If ca53_cpu.sdc supports a parameterized clock period (e.g., by checking if clk_period is already defined), you should set clk_period before sourcing the SDC. If it does not, you may need to manually re-apply the input/output delays and other clock-dependent constraints after redefining the clock to ensure they are not silently lost.

set clk_period 1550
source $::env(PLATFORM_DIR)/ca53_cpu/sdc/ca53_cpu.sdc

export SYNTH_NETLIST_FILES = $(PLATFORM_DIR)/$(DESIGN_NAME)/rtl/ca53_cpu.v

export SDC_FILE = $(PLATFORM_DIR)/$(DESIGN_NAME)/sdc/ca53_cpu.sdc
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/ca53/constraint.sdc

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@maliberty this was a workaround to change the clock period without touching the platform files. Let me know if I should change directly there.

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🔍 QoR check

Metrics reflect the PR merge build — i.e. what will land on the target branch.

Commit bf0089a · Jenkins build #1 · Baseline: build · View build on dashboard

62 design(s) checked — 0 with regression(s), 0 without a comparable baseline.

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2 participants