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gf12: tighten ibex and ca53 clock periods so setup WS < 0 - #4702
eder-matheus wants to merge 2 commits into
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Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
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This pull request updates the SDC file path and constraints for the ca53 design, and adjusts the clock period and slack margins for the ibex design. A critical issue was identified in the new ca53 constraint file, where redefining the clock after sourcing the base SDC can invalidate existing clock-associated constraints in STA tools. It is recommended to set the clock period before sourcing the base SDC.
| source $::env(PLATFORM_DIR)/ca53_cpu/sdc/ca53_cpu.sdc | ||
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| set clk_period 1550 | ||
| create_clock -name clk -period $clk_period [get_ports clk] |
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Redefining a clock using create_clock after sourcing the base SDC (ca53_cpu.sdc) can be highly problematic in STA tools like OpenSTA. When create_clock is called on an existing clock port/name, the tool destroys the original clock object and creates a new one. This action typically clears or invalidates any clock-associated constraints (such as set_input_delay, set_output_delay, set_clock_uncertainty, or set_clock_latency) that were defined in ca53_cpu.sdc and bound to the original clock.
If ca53_cpu.sdc supports a parameterized clock period (e.g., by checking if clk_period is already defined), you should set clk_period before sourcing the SDC. If it does not, you may need to manually re-apply the input/output delays and other clock-dependent constraints after redefining the clock to ensure they are not silently lost.
set clk_period 1550
source $::env(PLATFORM_DIR)/ca53_cpu/sdc/ca53_cpu.sdc
| export SYNTH_NETLIST_FILES = $(PLATFORM_DIR)/$(DESIGN_NAME)/rtl/ca53_cpu.v | ||
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| export SDC_FILE = $(PLATFORM_DIR)/$(DESIGN_NAME)/sdc/ca53_cpu.sdc | ||
| export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/ca53/constraint.sdc |
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@maliberty this was a workaround to change the clock period without touching the platform files. Let me know if I should change directly there.
🔍 QoR checkMetrics reflect the PR merge build — i.e. what will land on the target branch. Commit 62 design(s) checked — 0 with regression(s), 0 without a comparable baseline. |
gf12/ibex
only times the BC corner, so the margins over-repaired at BC without
closing WC. Removing them cut area 18%, power 32% and flow runtime
from 966 s to 307 s.
Finish: setup WS -34 ps, TNS -9.4 ns (493 endpoints), hold clean, 0 DRC.
gf12/ca53
Point SDC_FILE to it. The platform SDC is unchanged.
Finish: setup WS -98.6 ps, TNS -0.8 ns (16 endpoints, worst is a
clock-gate enable path), 0 DRC. Hold WS -25 ps (-15 ps in CI before).