[dhgaddy]

Summary

• Adds snitch_cluster to the gt2n platform (already on asap7/nangate45).
• Reaches _final. Setup clean (WNS +9.02ps). Hold has 9 residual
  violations (worst -8.56ps, TNS -25.89ps) -- see DECISIONS.md.

QoR summary

Design	Fmax	Die area (µm²)
snitch_cluster	166.7 MHz	308882

[mguthaus]

Thanks @dhgaddy. One blocker before this can go in: the +19k lines here are vendored RTL, and the suite has moved to hermetic, reproducible RTL sourcing — pinned http_archive stanzas in MODULE.bazel (bender-bypass), see #226–#230. snitch_cluster is already sourced hermetically for asap7/nangate45 (#227), so the gt2n port should reuse that pinned-archive RTL path rather than committing the generated .sv. Could you rework it to pull the RTL via the existing hermetic source and keep only the gt2n-specific config (BUILD.bazel, constraint.sdc, DECISIONS.md)? Happy to help wire it up.

[dhgaddy]

Perhaps I am mistaken, but I believe this port is already using hermetic sourcing. I did not commit snitch_cluster.sv and I just verified the BUILD.bazel points to the right place, like my other hermetic ports: verilog_files = ["//designs/src/snitch_cluster:rtl"] The 19k+ lines are almost all from fakeram generated macros. Please let me know if there is something I am misunderstanding!

[mguthaus]

You're right, @dhgaddy — my mistake, retracting the hermeticity blocker. I re-checked the diff: no vendored RTL, verilog_files points at the hermetic //designs/src/snitch_cluster:rtl, and the +19k lines are the fakeram LEF/LIB macros, which we commit for every design. I also spot-checked the generated macros and they're clean: wd_in pin directions are correct (post-c83ecb4 generator), and the cfg uses the camelCase snap keys with SIZE 117.390 BY 36.720 landing exactly on the 0.042/0.144 µm gt2n grid.

The residual hold violations are fine as documented in DECISIONS.md.

One change requested before merge: macro naming. The gt2n convention is a plain fakeram_ prefix (see the NVDLA gt2n cfgs); fakeram7_ is asap7's. I realize the fakeram7_* names are baked into the shared tc_sram.sv mapping (nangate45 reuses them too), so the clean fix is a snitch-wide rename to a platform-neutral fakeram_* prefix: update tc_sram.sv and the three fakeram cfgs, then regenerate the LEF/LIB via tools/regenerate_sram.sh (cheap — no synthesis). Doing it across all three platforms in this PR is the simplest route since the RTL mapping is shared.

[mguthaus]

Update on the naming request: since the fakeram7_* names were baked into the shared tc_sram.sv (nangate45 shipped them too), I've done the snitch-wide rename myself in #248 — tc_sram.sv + cfgs now use the platform-neutral fakeram_* prefix, with asap7/nangate45 LEF/LIB regenerated (asap7 also got the standard sram/{lef,lib} layout and the camelCase snap-grid-key fix).

Once #248 merges, this PR just needs the mechanical follow-through on gt2n: rename the macros in fakeram_gt2n.cfg to fakeram_*, rerun tools/regenerate_sram.sh snitch_cluster gt2n, and commit the renamed LEF/LIB (the rebased tc_sram.sv will already instantiate the new names). Everything else here looked good on re-review, so that should be the last change before merge.

[dhgaddy]

Ready on my end once #248 merges

[mguthaus]

#248 is merged (ternip got the same cleanup). @dhgaddy this is now unblocked — after rebasing on main, the only change needed here is the mechanical gt2n regen: rename the four macros in fakeram_gt2n.cfg to fakeram_*, rerun tools/regenerate_sram.sh snitch_cluster gt2n, and commit the renamed LEF/LIB. Ping me when it's pushed and I'll merge.

[dhgaddy]

@mguthaus should be good now