[mguthaus]

Summary

• Renames snitch_cluster's SRAM macros from the asap7-style fakeram7_* to the platform-neutral fakeram_* prefix, suite-wide (shared tc_sram.sv mapping + cfgs + regenerated LEF/LIB on asap7 and nangate45). Prompted by gt2n: port snitch_cluster #240, where the gt2n port inherited the misleading 7.
• Same cleanup for ternip (all three platforms): fakeram7_512x16 → fakeram_512x16, and the shared memory wrapper moves to its platform-neutral home designs/src/ternip/ternip_pipelined_mem_fakeram.v (nangate45/sky130hd were referencing it under designs/asap7/).
• Normalizes snitch-asap7 to the standard macro layout: cfg at dev/generated/fakeram_asap7.cfg, committed LEF/LIB at designs/asap7/snitch_cluster/sram/{lef,lib}/, local filegroups like the other platforms; the tracked dev/generated/sram/ tree is removed and tools/regenerate_sram.sh now works for both designs on every platform.
• Fixes the snitch + ternip asap7 cfgs' snake_case snap-grid keys (snap_width_nm → snapWidth_nm, the known silently-ignored-snap bsg_fakeram bug): macros now land exactly on the 0.190/1.400 µm site grid.

Verification

• snitch nangate45 LEF/LIB: byte-identical except the names. ternip nangate45/sky130hd: identical sizes/pins; internal PG-strap offsets shift ~1.1 µm because the committed LEFs predated the current bsg_fakeram pin (2db2c32).
• asap7 macros regenerated on-grid; size deltas negligible (<0.5 % per side).
• All wd_in pins DIRECTION INPUT (post-c83ecb4 generator); only rd_out is OUTPUT.
• bazel build --nobuild analysis passes for all five _synth targets; no fakeram7 references remain under designs/.

Fallout

• Macro names are bazel inputs, so snitch (asap7/nangate45) and ternip (all three) cached results invalidate and rebuild — accepted cost. snitch re-validation k8s jobs are running on this branch; ternip rebuilds go on k8s after merge.
• gt2n: port snitch_cluster #240 (gt2n port) regenerates its macros with the new names once this lands; the gt2n cfg rename is mechanical.